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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PECL PLL Clock Driver
The MPC992 is a 3.3V compatible, PLL based PECL clock generator and distributor. The fully differential design ensures optimum skew and PLL jitter performance. The performance of the device makes the MPC992 ideal for workstations, main frame computer, telecommunication and instrumentation applications. The device offers a crystal oscillator or a differential PECL reference clock input to provide flexibility in the reference clock interface. All of the control signals to the MPC992 are LVTTL compatible inputs.
MPC992
LOW VOLTAGE PLL CLOCK DRIVER
* * * * * * *
Fully Integrated PLL Output Frequency of up to 400MHz PECL Clock Inputs and Outputs Operates from a 3.3V VCC Supply Output Frequency Configurable 32 TQFP Packaging 25ps Cycle-Cycle Jitter
FA SUFFIX PLASTIC TQFP PACKAGE CASE 873A-02
The MPC992 offers two banks of outputs which can be configured into four different relationships. The output banks can be configured into 2:1, 3:1, 3:2 and 5:2 ratios to provide a wide variety of potential frequency outputs. In addition to these two banks of outputs a synchronization output is also offered. The SYNC output will provide information as to the time when the two output banks will transition positively in phase. This information can be important when the odd ratios are used as it provides for a baseline point in the system timing. The SYNC output will pulse high for one Qa clock period, centered on the rising Qa clock edge four edges prior to the Qb synchronous edge. The relationship is illustrated in the timing diagrams in the data sheet. The MPC992 offers several features to aid in system debug and test. The PECL reference input pins can be interfaced to a test signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in a system functional debug mode. In addition an overriding reset is provided which will force all of the Q outputs LOW upon assertion. The MPC992 is packaged in a 32-lead TQFP package to optimize both performance and board density.
MPC992 LOGIC DIAGRAM
PLL_EN VCO_SEL XTAL_SEL XTAL1 XTAL2 PECL_CLK PECL_CLK FSEL0 FSEL1 POR XTAL OSC x2 1 0 Integrated PLL 0 1 0 1
Qan Qan Frequency Generator Qbn Qbn SYNC SYNC
(x4)
(x3)
Reset
(x1)
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(c) Motorola, Inc. 1996
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VCCO1 VCCO2 17 16 15 14 13 Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 PLL_EN GNDI 12 11 10 9 1 2 3 4 5 6 7 8 XTAL2 SYNC 19 PECL_CLK SYNC 18 XTAL1
Qa2
Qa2
Qa3 21 XTAL_SEL
24 Qa1 Qa1 Qa0 Qa0 GNDA VCCA Reset VCCI 25 26 27 28
23
22
20
MPC992
29 30 31 32
FUNCTION TABLE 1
FSEL0 0 0 1 1 FSEL1 0 1 0 1 Qa VCO/4 VCO/2 VCO/4 VCO/2 Qb VCO/6 VCO/4 VCO/10 VCO/6 Feedback VCO/24 VCO/16 VCO/40 VCO/24 Ratio 3:2 2:1 5:2 3:1
PECL_CLK
VCO_SEL
FSEL0
FSEL1
Qa3
FUNCTION TABLE 2
Control Signal Reset XTAL_SEL PLL_EN VCO_SEL Logic `0' Outputs Enabled PECL REF Disabled High Frequency Logic `1' Outputs Disabled XTAL REF Enabled Low Frequency
INPUT vs OUTPUT FREQUENCY
FSEL0 0 0 1 1 FSEL1 0 1 0 1 Qa 6 (fref) 8 (fref) 10 (fref) 12 (fref) Qb 4 (fref) 4 (fref) 4 (fref) 4 (fref) Int Feedback fref fref fref fref
PIN DESCRIPTION
Pin Name VCO_SEL PLL_EN XTAL_SEL XTAL1:2 PECL_CLK PECL_CLK FSELn RESET Function VCO range select pin (Int Pullup) PLL bypass select pin (Int Pullup) Input reference source select pin (Int Pullup) Crystal interface pins for the internal oscillator True PECL reference clock input (Int Pulldown) Compliment PECL reference clock input (Int Pullup) Internal divider select pins (Int Pullup) Internal flip-flop reset, true outputs go LOW (Int Pulldown)
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TIMING SOLUTIONS BR1333 -- REV 5
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2:1 Mode Qa
Qb
SYNC
3:1 Mode Qa
Qb
SYNC
3:2 Mode Qa
Qb
SYNC
5:2 Mode Qa
Qb
SYNC
Figure 1. Output Waveforms
ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VI IOUT TStor Supply Voltage Input Voltage Output Current Storage Temperature Range Continuous Surge -40 Parameter Min -0.3 -0.3 Max 4.6 VDD + 0.3 50 100 125 Unit V V mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
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MPC992
DC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%)
Symbol VIH VIL VOH VOL IIN ICCI Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage1 Output LOW Voltage1 Input Current Maximum Quiescent Supply Current PECL_CLK1 Other PECL_CLK1 Other Min 2.15 2.0 1.5 0 1.8 1.2 -120 130 15 Typ Max 2.4 VCC 1.8 0.8 2.4 1.7 120 150 20 Unit V V V V A mA mA Condition VCC = 3.3V VCC = 3.3V VCC = 3.3V VCC = 3.3V
ICCA Maximum PLL Supply Current 1. DC levels will vary 1:1 with VCC.
AC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 5%)
Symbol tr, tf tpw1 tpw2 fref tos fVCO fmax Characteristic Output Rise/Fall Time Output Duty Cycle SYNC Output Duty Cycle Input Reference Frequency Output-to-Output Skew PLL VCO Lock Range Maximum Output Frequency Qa (/2) Qa,Qb (/4) Qb (/6) Qb (/10) 25 Xtal FREF Min 200 49 0.95 10 Note 2 Typ Max 850 51 1.05 20 Note 2 100 300 200 400 440 750 375 187.5 125 75 50 Unit ps % % MHz ps MHz MHz VCO_SEL = 1 VCO_SEL = 0 Note 1 PCLK Period Condition 20% to 80%
Qa, Qb Qa (-) to SYNC (+)
tjitter
Cycle-to-Cycle Jitter (Peak-to-Peak)
ps ms
Note 3
tlock Maximum PLL Lock Time 10 1. At 400MHz the output swing will be less than the nominal value. 2. ECLK and XTAL input reference limited by the feedback divide and the guaranteed VCO lock range. 3. Guaranteed by characterization.
APPLICATIONS INFORMATION
Using the On-Board Crystal Oscillator The MPC992 features an on-board crystal oscillator to allow for seed clock generation as well as final distribution. The on-board oscillator is completely self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC992 as possible to avoid any board level parasitics. To facilitate co-location surface mount crystals are recommended, but not required. The oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this
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eliminates the need for large on-board capacitors. Because the design is a series resonant design, for optimum frequency accuracy a series resonant crystal should be used (see specification table below). Unfortunately most off the shelf crystals are characterized in a parallel resonant mode. However a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel resonant mode. Therefore in the majority of cases a parallel specified crystal can be used with the MPC992 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. Typically
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a parallel specified crystal used in a series resonant mode will exhibit an oscillatory frequency a few hundred ppm lower than the specified value. For most processor implementa- tions a few hundred ppm translates into kHz inaccuracies, a level which does not represent a major issue. Figure 2 shows an optional series capacitor in the crystal oscillator interface. The on-board oscillator introduces a small phase shift in the overall loop which causes the oscillator to operate at a frequency slightly slower than the specified crystal. The series capacitor is used to compensate the loop and allow the oscillator to function at the specified crystal frequency. If a 100ppm type error is not important, the capacitor can be left off the PCB. For more detailed information, order Motorola Application Note AN1579/D.
MPC992 XTAL1
Figure 3 illustrates a typical power supply filter scheme. The MPC992 is most susceptible to noise with spectral content in the 10kHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC992. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 3 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20KHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL.
XTAL2 CTUNE (Optional) 3.3V
Figure 2. Recommended Crystal Interface
RS=10-15 VCCA
Table 1. Crystal Specifications
Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance* 75ppm at 25C 150ppm 0 to 70C 0 to 70C 5-7pF 50 to 80 max 100W 5ppm/Yr (First 3 Years)
22F MPC992 VCC 0.01F 0.01F
Figure 3. Power Supply Filter A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000H choke will show a significant impedance at 10KHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCCA pin a low DC resistance inductor is required (less than 15). Generally the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. The MPC992 provides sub-nanosecond output edge rates and thus a good power supply bypassing scheme is a must. The important aspect of the layout for the MPC992 is low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the MPC992 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the
Power Supply Filtering The MPC992 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC992 provides separate power supplies for the digital circuitry (VCCI) and the internal PLL (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC992.
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capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. No active signal lines should pass below the crystal interface to the MPC992. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on-board oscillator. In addition, the crystal interface circuitry will be adversely affected by activity on the PECL_CLK inputs. Therefore, it is recommended that the PECL input signals be static when the crystal oscillator circuitry is being used. Although the MPC992 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
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OUTLINE DIMENSIONS
FA SUFFIX PLASTIC TQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS BR1333 -- REV 5
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
7
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z- MOTOROLA
MPC992
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*MPC992/D*
MPC992/D TIMING SOLUTIONS BR1333 -- REV 5

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